Grader

Tingting Sun

Email: sunting AT winlab.rutgers.edu

Class Meeting Time and Place

Wed 6:40pm-9:20pm

SEC-207, Busch

Prerequisite

Undergraduate level Computer Architecture. Familiar with datapath and control design, instruction sets, pipelined datapath and pipeline hazards, memory hierarchy, cache organization.

Required Textbooks

J. L. Hennessy & D. A. Patterson, Computer Architecture, A Quantitative Approach, Fourth Edition, Morgan Kaufman, 2006 (Significantly different from earlier versions. Earlier versions are NOT recommended!)

Topics to Be Covered

Computer Performance · Pipelining · Instruction-level Parallelism (VLIW) · Multiprocessors · Thread-level Parallelism · Multi-core · Memory Hierarchy · Storage System · Embedded Systems

Grading Policy

Midterm Exam: 30%

Paper Summaries: 15%

Class Participation: 5%

Term Project: 50%

Paper Reading

Every week, you will be assigned two papers to read. The papers will be discussed in class. Students will take turns to lead the discussion. You are also required to write a half page summary for each paper, which should answer a set of questions.

Exams

One midterm exam and no final exam. The midterm exam will be in-class, closed-book, no calculator/computer allowed.

Projects

A major component of this class is a term project. By the end of this semester, you will be required to write a conference-style paper with a clearly-stated problem, a well thought-out solution, and a comprehensive evaluation. A set of project subjects will be provided on the class website in the first few weeks. You are also encouraged to come up with your own topics. The hope is that Ph.D. students can have your first publication, while M.S. students can have your thesis written up in the class.